One of the original goals of Verilog-AMS was to work with purely digital design using standard RTL synthesis with cell libraries in order to support verifying techniques like DVFS. That would be achieved by inserting A/D conversions at inputs and outputs of the logic cell digital models, and using analog wiring in back-annotation rather than SDF (which is fixed Voltage).
Since the cell libraries are delivered well before designs get going, there is plenty of time to characterize the individual pins on cells, and the discipline class hierarchy lets you have as many pin types as needed. You can then create connection rules based on the disciplines to insert the right A2D or D2A connect-module if a cell port is connected to something analog (in the absence of analog components it will stay digital). I.e. all you should need to do is back-annotate with SPEF to get the more accurate simulation. Of course the connect-modules need power connections to get the right Voltage levels, and they get those through cross-module references (scoping up).
Or rather, that was the way it was supposed to work, however misplacing of the connect-modules and the lack of support for SPEF back-annotation into behavioral code means nobody has implemented it – but you can make it work very similarly with some extra scripting (get in touch if you want to know how).
In addition to DVFS, the techniques work for factoring in body-biasing and thermal issues.
Mea Culpa
Another reason it has not been automated is “premature optimization”, when this methodology was originally proposed someone complained that there would be too many A2D and D2A elements if every cell port had one, so I added a “merged” connect-module capability. While that’s easier for people to use, it’s a lot harder to automate. The un-merged version can be reduced to something simpler in compilation if the modeling is done in a way that is suitable.
Notes
If you are wondering about the change in logic speed as Voltage drops with DVFS, you can ignore that in the digital model and just use a fast version, the de-rating is done in the connect-modules.