Cameron EDA
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Sv2gHDL/vamos – overarching project
Simulators
Modified versions supporting federation, AMS/RF and FPGA/GPU acceleration.
nvc
Added a new resolution scheme to support mixed types on a wire, federation, bidirectional components.
New type libraries – a 3D logic family to kill the X-prop problem.
iverilog
Extensions for use as a SystemVerilog/Verilog-AMS front-end to nvc/xyce.
xyce
Replaced ADMS with PyMS
vacask
Mixed-signal bridges.
General
smak
A replacement for make/cmake, compute farm aware, works as a persistent server noticing changes through Fuse.