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Having worked in parallel computing for decades, I’ve seen a number of interesting processors arrive and then die due to lack of a usable software methodology or a way to run legacy code. GPUs and FPGAs have squeezed by, but are not invulnerable. I thought I’d do a list, and if you don’t want to…

One of the original goals of Verilog-AMS was to work with purely digital design using standard RTL synthesis with cell libraries in order to support verifying techniques like DVFS. That would be achieved by inserting A/D conversions at inputs and outputs of the logic cell digital models, and using analog wiring in back-annotation rather than…

As a methodology RTL (register transfer level) has been around for about three decades, and there are many digital design tools that understand it. However, as an approach to digital design it has an underlying assumption that transistors are well-behaved and you can fiddle with gate sizes and implementation to line up timing on a…

The standard way of accessing common code and services is an API – the application programming interface. APIs tend to become a boat-anchor in code, once you use one you are dependent on its particular way of doing things. They are opaque portals. Languages describe how to do something, e.g. regular style linear (control flow)…

Verilog-AMS has its roots in a battle between Spectre-HDL and MAST, two analog behavioral languages that went looking for standards backing in the early 1990s. Analogy took Mast to the IEEE and Cadence took Spectre’s HDL to OVI (the body that standardized Verilog). MAST ended up as a little used add-on to VHDL, with no…

Clock domain crossing errors are impossible to simulate in old Verilog simulators, the reason being that signals are processed sequentially and can only have 0/1 values, so can never be coincident. Consequently most CDC tools only do static analysis. Back around 2000 a company came up with a way of simulating variable timing called “histogram…