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Verilog-AMS has its roots in a battle between Spectre-HDL and MAST, two analog behavioral languages that went looking for standards backing in the early 1990s. Analogy took Mast to the IEEE and Cadence took Spectre’s HDL to OVI (the body that standardized Verilog). MAST ended up as a little used add-on to VHDL, with no…

Clock domain crossing errors are impossible to simulate in old Verilog simulators, the reason being that signals are processed sequentially and can only have 0/1 values, so can never be coincident. Consequently most CDC tools only do static analysis. Back around 2000 a company came up with a way of simulating variable timing called “histogram…