Author: admin

I’ve recently been looking at building a robot for EV charging, here are a couple of examples – These robots fail because the designers are trying to make a robot do something the way a human would do it. Robots can be any size and shape, they can have multiple limbs or none, and they…

For as long as people have used Verilog, dealing with Xs in models has been a problem – The root of that was wanting a simple signal model that wouldn’t take up much memory in the early Verilog simulators – cache performance being a major determinant of simulation speed, so packing 0,1,X,Z into 2-bits worked…

[A different perspective to http://parallel.cc] So the genesis of WT was the realization (after working on it for a year or more) that the maximum speed up on SMP for VCS was going to be ~4x. Two decades on Synopsys don’t seem to be doing much better than that (at 5x)- https://news.synopsys.com/2016-03-24-Synopsys-Unveils-Breakthrough-Parallel-Simulation-Performance-Technology-for-VCS (the gate level…

A while back I worked out what the minimum extensions to C++ would be for making it easy to model hardware, you can find that at http://parallel.cc. In a similar vein I wondered what the minimum extension to an analog simulator would be to support mixed-signal simulation, and that one turns out to be programmable…

[In case you feel I’m being hard on VCS-AMS, the same failings apply to offerings from other major EDA vendors] Digital-on-top AMS simulators don’t work For a mixed signal simulator to work properly all the wiring needs to be analog so that all analog things attached to a wire can be computed together. Digital-on-top simulators…

Most computer scientists are familiar with Amdahl’s Law, boiled down it says the fastest your program can run is determined by the slowest of the parallel threads (assuming you can decompose it into parallel threads). However, it says little about the decomposition, and assumes that your threads have equal resources (assuming an SMP environment). If…

Having worked in parallel computing for decades, I’ve seen a number of interesting processors arrive and then die due to lack of a usable software methodology or a way to run legacy code. GPUs and FPGAs have squeezed by, but are not invulnerable. I thought I’d do a list, and if you don’t want to…

One of the original goals of Verilog-AMS was to work with purely digital design using standard RTL synthesis with cell libraries in order to support verifying techniques like DVFS. That would be achieved by inserting A/D conversions at inputs and outputs of the logic cell digital models, and using analog wiring in back-annotation rather than…

As a methodology RTL (register transfer level) has been around for about three decades, and there are many digital design tools that understand it. However, as an approach to digital design it has an underlying assumption that transistors are well-behaved and you can fiddle with gate sizes and implementation to line up timing on a…

The standard way of accessing common code and services is an API – the application programming interface. APIs tend to become a boat-anchor in code, once you use one you are dependent on its particular way of doing things. They are opaque portals. Languages describe how to do something, e.g. regular style linear (control flow)…