Verilog-AMS has its roots in a battle between Spectre-HDL and MAST, two analog behavioral languages that went looking for standards backing in the early 1990s. Analogy took Mast to the IEEE and Cadence took Spectre’s HDL to OVI (the body that standardized Verilog).
MAST ended up as a little used add-on to VHDL, with no analog/digital connection automation. While Cadence were looking for something similar they were told “Verilog-A” would only be accepted as part of a fully integrated Verilog-AMS (i.e. all Verilog, new analog language and MS-glue).
Although Verilog-AMS was designed to fulfill OVI’s goal, that didn’t quite work for Cadence, who realigned the standard to match existing product, then refused to implement key parts (removing them from the LRM), they then held up full integration and Verilog-AMS got left behind at Accellera (the renamed OVI), while digital Verilog moved to the IEEE.
Since then very little progress has been made in mixed-signal simulation.